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Electrical Properties of Surface-Passivated GaAs Nanowires
Applied Science and Convergence Technology 2018;27:166-168
Published online November 30, 2018;  https://doi.org/10.5757/ASCT.2018.27.6.166
© 2018 The Korean Vacuum Society.

Rochelle S. Leea, Tae Kyum Kimb, Sang Won Leeb, Kyu Yeon Chob, Jong Hyun Choib, Mi Yeong Kimb, and Jae Cheol Shina,*

aDepartment of Physics, Yeungnam University, Gyeongsangbuk-do 38541, Republic of Korea, bDaegu Science High School, Daegu, Republic of Korea
Correspondence to: *Corresponding author: E-mail: jcshin@yu.ac.kr
Received November 20, 2018; Accepted November 23, 2018.
Abstract

The electrical properties of surface-passivated GaAs nanowires (NWs) were investigated and compared with those of unpassivated NWs. Surface passivation was carried out by chemically etching the native oxide of the GaAs NWs with ammonium polysulfide, (NH4)2Sx, while the native oxide of the unpassivated NWs was etched in hydrochloric acid solution. The GaAs NWs were grown by metal-organic chemical vapor deposition via a Au-catalyzed vapor-liquid-solid growth method. Sulfur-passivated single-GaAs NWs showed 3-fold increase in mobility, indicating that sulfur passivation reduces the presence of surface states, contact resistance, and the Schottky barrier at NW-metal contacts.

Keywords : GaAs nanowires, Sulfur passivation, Metal-organic chemical vaper deposition, Nanowire-based field effect transistor
I. Introduction

Semiconductor nanowires (NWs) are promising for use in optoelectronic devices due to their two-dimensional quantum confinement effects and one-dimensional transport properties [14]. Among semiconductor NWs, GaAs NWs have promising optoelectronic applications because of their high absorption coefficient [5], low auger recombination rate [6,7], and high electron mobility [8,9]. Furthermore, GaAs semiconductors have been one of the most widely used semiconductors for applications in fast electronics, infrared light-emitting diodes, and high-efficiency solar cells [10]. GaAs, however, suffer from high surface recombination velocity (~106 cm/s), which is three orders of magnitude higher than those of most other III-V semiconductors [11]. The surface recombination velocity is directly linked to the presence of surface states [12,13]. The presence of surface states strongly affects the electron transport properties in semiconductors, resulting in a reduction in device performance [12,14]. Furthermore, the presence of surface states can drastically reduce carrier lifetimes, as reflected by the reduced photoluminescence intensity of GaAs NWs [11]. It has been reported that sulfur treatment can significantly reduce the number of surface states of GaAs [12,1519]. Sulfurization removes the native oxide from the surface and encourages reaction of sulfur with semiconductor atoms. Sulfur passivation in GaAs leads to complete removal of the oxide layer and formation of As-S and Ga-S bonds [20]. Hence, the dangling bonds of the sulfur-passivated GaAs surface are significantly weaker than those of unpassivated surface. In this study, current-voltage (I–V) characterizations of sulfur-passivated GaAs NWs were investigated and compared with those of unpassivated NWs. The sulfur-passivated GaAs NW-based field-effect transistor (FET) showed a 3-fold increase in mobility compared to the unpassivated GaAs NW-based FET.

II. Experimental details

A horizontal reactor metal-organic chemical-vapor-deposition (MOCVD) system (AIXTRON A200) was used to grow the GaAs nanowires. In the beginning, a 2-in GaAs (111) wafer was dipped in hydrochloric acid solution to remove native oxide on the surface. Immediately after rinsing and drying with deionized water (DI) and nitrogen gas, respectively, the wafer was loaded into the MOCVD reactor. At a reactor temperature of 650 °C, arsine (AsH3) and trimethylgallium (TMGa) was flowed to grow the GaAs NWs. The morphology and structure of the GaAs NWs were examined by transmission electron microscopy (TEM), as shown in Fig. 1. For the mobility measurement, NWs were removed from the growth substrate by sonication in isopropyl alcohol for 30 s, followed by random dispersion onto a heavily doped silicon substrate covered by thermally grown 300-nm-thick silicon dioxide (SiO2). Then, the native oxide on the NW surface was removed by dipping the sample in HCL:DI (1:1) solution for 10 s. Thereafter, passivation was performed by soaking the NWs in ammonium sulfide (NH4)2Sx for 5 min. The sulfide solution was prepared by adding 0.5 g of elemental sulfur to 5 ml of (NH4)2S (24 %). Then, 1 ml of the new (NH4)2Sx solution was diluted in 9 ml of DI water. Photolithography was conducted immediately after passivation to define source-drain electrodes on the NW. Later Ge/Au/Ni/Au (26/54/15/180 nm) metal was deposited by an electron-beam evaporator onto the sample. Finally, a lift-off process was performed in which the degenerately p-doped Si substrate provided a back gate, as depicted in Fig. 2(b). The passivation effect was investigated by measuring the I–V curve, using a four-probe station (ETCP-2000, ECOPIA InC).

III. Results and discussion

The TEM images of MOCVD-grown GaAs NWs are shown in Fig. 1. The TEM image allows the analysis of the NW crystal structure. In Fig. 1(a), the nanowire appears with a zinc blende (ZB) crystal structure, with very low stacking faults. The inset in Fig. 1(c) shows the fast-Fourier-transform (FFT) ZB pattern. In Fig. 2(b), an Au nanoparticle is visible at the nanowire top. The Au nanoparticle at the apex indicates that the growth is carried out via the vapor-liquid-solid growth (VLS) mechanism [21]. Figure 1(c) is a high-resolution TEM image, which further illustrates the absence of twin planes or stacking faults.

The SEM images in Fig. 2(a) shows the GaAs NW-based device (length: L = ~2.6 μm and radius: r = ~50 nm) fabricated on an Si substrate with a 300-nm-thick SiO2 layer. Figure 2(b) presents a schematic of the GaAs NW FET with a back gate.

The electrical properties of passivated GaAs NWs, I–V characteristics for a sulfur-passivated NW [Figs. 3(a) and 3(b)], and non-passivated NW [Figs. 3(c) and 3(d)] were measured. The output characteristics are shown in Figs. 3(a) and 3(c). The I–V curve is not linear, indicating the presence of a high Schottky barrier. Furthermore, the extracted peak current is low in the range of pA. However, the sulfur-passivated NW shown in Fig. 3(a) exhibits higher current, compared to unpassivated NW [Fig. 3(c)], as the current for a 10-V bias is twice that of the passivated device. From Figs. 3(b) and 3(d) the nanowires exhibit p-type behavior, illustrating that a majority of carriers in our device are holes, as evident from the decrease in Ids with increasing gate bias.

The hole mobilities were extracted from the passivated [Fig. 3(b)] and unpassivated device [Fig. 3(d)] at room temperature (300 K). The hole mobility was estimated using Eq. (1) in the linear region of the Ids-Vbg curves [22].

μ=gm(L2Cox)(1Vds)

where Cox was calculated from the expression

Cox=(2πɛɛ0Lcosh-1|r+toxr|)andgm=(dIdsdVbg)|Vds.

Transconductance is represented by gm, extracted from the slope of the linear region, at a Vds of 5 V, L is the channel length of the device (2.6 μm), Cox is the back-gate capacitance, r is the radius of the NWs (~50 nm), tox is the thickness of SiO2 layer (300 nm), ɛ is the permittivity of free space (8.85 × 10−14 F/cm), and ɛ0 is the permittivity of SiO2 (3.9). The calculated carrier mobility was found to be 4.4 × 10−4 cm2/Vs and 1.3 × 10−4 cm2/Vs for the sulfur-passivated and unpassivated NWs, respectively. Due to the presence of the high Schottky junction between the NW and the electrode, the calculated field-effect mobility is quite low. The existence of the Schottky contacts prohibits the reliable estimate of the mobility provided by the transconductance [12]. Even after the surface passivation by sulfur, the measured mobility is not comparable to the bulk mobility for core-shell structured GaAs NWs [23,24], probably due to the low carrier concentration of charge carriers in our GaAs NWs. It is found that the carrier concentration and mobility share a directly proportional relationship; thus, higher carrier concentration (within a limit) results in a linear increase in mobility [25,26]. Moreover, low background doping in the grown GaAs NWs means fewer carriers available for conduction. In addition, devices passivated by ammonium polysulfide solution tend to degrade after several measurements. Nonetheless, it is evident from measurements that the sulfur-passivated device exhibited higher conductivity and mobility. The passivated NW-based FET exhibited a 3-fold increase in mobility. This is probably because of reduced surface states and a decrease in fermi-level pinning at the oxide surfaces [27]. Fermi-level pinning in low-doped GaAs NWs can completely switch off the conductivity along the nanowire. In addition, a reduction in the Schottky barrier height at the metal-semiconductor interface decreases the NW contact resistance [28]. To improve the mobility in GaAs nanowires, metal deposition should be performed directly after sulfur passivation, and GaAs nanowire samples should be kept under vacuum conditions directly after MOCVD growth and between electrical measurements. In addition, slight doping in NWs may help increase carrier concentration and, hence, mobility.

IV. Conclusions

The sulfur passivation effect of GaAs NWs was investigated by measuring the I–V characterization of GaAs NWs. Sulfur passivation on GaAs NWs was performed by chemically etching the native oxide with ammonium polysulfide solution, (NH4)2Sx. Sulfur-passivated GaAs NWs show 3-fold greater mobility than that of unpassivated NWs. The GaAs NWs were grown by MOCVD via the Au-catalyzed VLS method.

Acknowledgments

This work was supported by the National Research Foundation of Korea (NRF-2017R1C1B2010906).

Figures
Fig. 1. TEM analysis of GaAs NW grown by MOCVD. (a) Low-resolution TEM image showing NW surface morphology; (b) low-resolution TEM image showing NW tip, with Au nanoparticle at nanowire apex; and (c) high-resolution TEM image showing zinc blende structure of GaAs NW, free of stacking fault, and inset showing FFT image of crystal structure.

Fig. 2. GaAs NW-based device. (a) Representative SEM image of fabricated NW device and (b) schematic illustration of the FET back gate device.

Fig. 3. Electrical characterization of passivated and non-passivated GaAs NW-based FET. (a), (c) Output characteristics showing the Ids-Vds behavior of passivated and unpassivated NWs, respectively, for zero gate bias; and (b), (d) transfer characteristics showing Ids-Vbg behavior of passivated and unpassivated FET at various Vds.

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