Fig. 1. (a) Optical image of graphene field effect transistor (FET) with Cr/Au electrodes contacts on the SiO₂ substrate. (b) Topography image of the dashed box shown in (a). (c) Enlarged topography image of the dashed box in (b), the height of bi-layer graphene and residues are marked by black and white arrows, respectively.

Applied Science and Convergence Technology 2020;29:180~182 https://doi.org/10.5757/ASCT.2020.29.6.180

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