Applied Science and Convergence Technology

Fig. 3. Conductance through device was calculated numerically using KWANT simulator. (a) Calculated results for 300 nm QD device. The upper and lower QD gate voltages were set to be different. The upper and the lower QD gate voltages were set to V_up = V_c, V_down = V_c − 0.03 V, respectively, while V_c was varied in 15 steps from -0.69 to -0.895 V. A small conductance bump (grey arrow) in the transition region evolved into a plateau as the 1D gate voltage changed. (b) Calculated results for 600 nm QD device. The upper and lower QD gate voltages were set to be identical, V_up = V_down = V_c, while V_c was varied in 15 steps from −0.42 to −0.7 V.

Applied Science and Convergence Technology 2023;32:19~22 https://doi.org/10.5757/ASCT.2023.32.1.19