In recent years, two-dimensional NAND flash memory innovation has transcended 20-nm technology. Nevertheless, there remain several challenges to scaling it down. The most critical issue arises when a small memory window of a tiny cell for multi-bit operation expands. The memory window width determines the charge trap density based on the floating gate material, coupling ratio, cell-to-cell interference, etc. [1−6]. Considerable effort has been devoted toward developing a structural approach for solving these issues to realize scaled NAND flash memory. Poly-Si has long been used as a floating gate in NAND flash memory owing to its favorable characteristics [7,8]. To enhance the property of a floating memory cell, we attempted to change the floating cell from Poly-Si to Poly-GaAs and reported our findings in a previous article [9]. GaAs is an attractive material owing to its electron speed, high charge trap density, and temperature immunity. However, its drawbacks are the dispersion phenomenon of arsenic at 600 ℃ and the large strain from the silicon substrate. Hence, we require an advanced material having a temperature endurance of greater than 700 ℃ and low silicon defect density. Gallium phosphide (GaP) has special properties such as a charge trap density of 10¹⁴–10¹⁶ cm^-3 measured using a current transient spectroscopy system [10], tem- perature immunity of greater than 750 ℃, and a mismatch density that is much lower than that of GaAs for the silicon-based material.

In this study, we evaluated a new material, namely polycrystalline gallium phosphide (Poly-GaP), at a low temperature. It is known that GaP provides excellent thermal endurability of greater than 750 ℃ and is highly compatible with CMOS. In addition, via C–V measurement, we discovered through intensive examination that Poly-GaP has a significant charge trap density that is equal to or greater than that of Poly-GaAs. With the expectation of higher trap densities in the vicinity of the interface between Poly-GaP and SiO₂ on a silicon substrate, the memory window of the III–V capacitor with a GaP floating gate was compared with that of a Poly-GaAs and Poly-Si floating gate [9] using C–V measurement. Thus, we confirmed the po sibility of a candidate material for microscopic NAND flash memory.

To obtain a high-quality Poly-GaP layer, the main chamber was kept in an ultra-high vacuum at 3 × 10^-10 Torr. The sample was loaded into the main chamber and a 0.5-μm-thick floating layer was grown at 1.82 Å/s, below 300 ℃, with an operation vacuum level of 3 × 10^-8 Torr and a 1 × 10^-5 Torr III–V (phosphorus or arsenic) beam source. SiO₂, as a block oxide, was deposited using a low-pressure chemical vapor deposition system. For the gate material, titanium (50 nm), as a barrier layer, and platinum (100 nm) were deposited by electron beam evaporation. For reference, three types of samples, namely Poly-GaAs, Poly-GaP, and Poly-Si, were planned and fabricated under the same geometric conditions t compare the characteristics of their memory window as a capacitor.

3.1. Device Characteristics

To confirm the polycrystallinity of GaP, the fast Fourier transformation (FFT) analytic technique was adopted with a high-resolution transmission electron microscopy (TEM) image at a scale bar of 50 nm. The GaP material a columnar structure [10].

Figure 1(a) shows an FFT pattern of Poly-GaP on the grown SiO₂/Si substrate. A device with a Poly-GaP floating gate with a grain boundary was presented and compared with the Poly-GaAs and a Poly-Si floating gates [7]. Further, as shown in Fig. 1(b), all the peaks of GaP were assigned to the zinc blend phase of GaP (JCPDS data: 01-071-5973). Analysis of the FFT pattern and X-ray diffraction (XRD) data suggested polycrystalline growth on SiO₂ [11−13]. From these results, we confirmed that Poly-GaP was grown successfully.

Figure 1. Cross-sectional TEM image of fabricated Poly-GaP device. (a) A P-type Si (100) wafer was prepared by pre-cleaning; then, thermal dry oxidation with a 10 nm thickness was performed at 900 ℃. A Poly-GaP layer was grown on SiO₂/p-type Si using a Riber Compact 21E solid source molecular beam epitaxy system. (b) The XRD pattern of the polycrystalline GaP layer is shown.

Figure 2 shows a cross-sectional TEM image of the capacitor with floating Poly-GaP. As seen in this figure, large distortions were found, such as vacancies or holes in Poly-GaP. These defects can capture charges and act as charge storage sources. We concluded that electrons are stored in the interface of both the materials [14,15]. Figure 3 shows the C–V characteristics of those cells whose III–V floating gates consist of a polycrystalline state. The C–V measurement was conducted using an Agilent/HP 8110A pulse generator

Figure 2. III-V memory structure using a Poly-GaP floating gate. Cross-sectional TEM image shows fabricated device. This structure consists of a metal gate, block oxide (50 nm), floating gate of Poly-GaP material (0.5 μm), and tunnel oxide (10 nm) on silicon substrate and the Poly-GaP layer has a columnar shape.

Figure 3. C-V characteristics of Poly-GaP, Poly-GaAs, and Poly-Si flash cells. (a) Average value of the memory window with 20 cell samples. (b) Shift of the flat band voltage (V_fb) with an applied sweep voltage from -24 to 24 V.

Figure 3(a) shows various C–V hysteresis curves of the Poly-GaP samples. The sweep bias range is ±21 V. The hysteresis of the larger memory window increases with the sweep gate bias. As shown in the inset, the memory window may become saturated. The memory window is approximately 6.67 V at a gate bias of ±21 V. In the case of Fig. 3(b), we show the most stable memory window; while Poly-Si is saturated to 3.2 V at a sweep bias of ±14 V, Poly-GaAs shows 5.6 V at a bias of ±22 V and Poly-GaP shows 6.67 V at a bias of ±21 V.

From these results, we confirmed that the window margin of the Poly-GaP material is 2.1 times larger than that of Poly-Si and 1.2 times larger than that of Poly-GaAs. We used the average value of the memory window of 20 cell samples with a sweep voltage ranging from -24 to 24 V. Thus, we confirmed that more than 70% of the measured cells have Poly-GaP at 6.67 V. Our structure is essential for the consideration of the block oxide (50 nm) because gate coupling is dependent on it. Further investigation is required for a capacitor using a III–V floating gate with a coupling ratio larger than 0.5 by applying a thinner block oxide (<10 nm).

In this paper, for the first time, we investigated how the memory window is related to the types of materials such as Poly-Si and Poly-GaAs in capacitors with Poly-GaP floating gates. Additionally, the memory window widths of III-Vs and Poly-Si are compared as a capacitor. The proposed Poly-GaP memory cells show a large memory window width of 6.67 V for the capacitor with a GaP floating gate, which is two times larger than that with a poly silicon floating gate. It has been confirmed that the window of the charge trap memory made using gallium phosphide exhibited better material characteristics, which led to significant improvement of the memory window. The proposed GaP growing method on silicon substrate is a very effective approach that results in better cell characteristics. A Poly-GaP is a good candidate material in nanoscale NAND flash memory due to the fact that it has resistant to high temperature and wider memory window.

Moreover, it is a more useful Nano technology because it is compatible with CMOS processes.

This research was supported by the Ministry of Trade, Industry & Energy (MOTIE (project number 20003808)) and Korea Semiconductor Research Consortium (KSRC) support program for the development of the future semiconductor device. The author from KIST acknowledges partial support from the KIST institutional program.