The development of Si technology for processors and memory units has been driven by the scaling down of transistors for better performance, lower power consumption, and higher density. As the channel length of Si metal-oxide-semiconductor field-effect transistors (MOSFETs) reaches its physical limit, however, it is no longer economically feasible to continue MOSFET scale-down [1,2]. Instead, the industry has been developing alternatives such as the through Si-via (TSV), which increases the device density without reducing MOSFET lateral size [3]. Vertically interconnecting devices using a TSV technique means more transistors can be stacked on existing transistors to increase number of devices per unit area. Transistors integrated in such a way are called back-end-of-line (BEOL) compatible transistors, in which ‘compatible’ means the process temperature should not exceed 400–450 °C to protect the underlying devices and interconnecting metals. This constraint on the thermal budget makes it difficult to form high-performance BEOL-compatible transistors by a direct deposition approach [2].

Amorphous/polycrystalline oxide semiconductors such as indium oxide (In₂O₃), indium-gallium-zinc oxide, and Sn-doped In₂O₃ have been extensively studied as channel layers for BEOL-compatible transistors because of their excellent electrical conductivity and low process temperature (< 400 °C) [4–6]. Some promising results have been reported on oxide FETs with current on/off ratio (I_ON/I_OFF) of > 107 and field-effect mobility of 10–20 cm²/Vs [5,7]. However, the scarcity of indium and complicated ternary or quaternary compositions make these oxides unattractive. Tin oxide (SnO and SnO₂) is also very attractive because of its large bandgap (3.6 eV) and high intrinsic electron mobility (200–300 cm²/Vs) [8,9]. Furthermore, SnO is known to exhibit p-type conductivity, which is an attractive property for complementary 3-dimensional circuit design [10–12].

One of the challenges of using oxide semiconductors, including SnO₂, is the doping controllability, because these materials typically contain 10²⁰–10²¹ cm⁻³ of electrons from unintentional doping by oxygen vacancies [4,13–15]. Such a high concentration of carriers makes channel modulation difficult and can adversely affect channel mobility due to limited channel thickness [5]. In this work, SnO₂ was deposited by thermal atomic layer deposition (T-ALD). A typical SnO₂ film deposited by T-ALD with H₂O reactant is quite resistive without post-annealing. Therefore, its carrier concentration and mobility can be tuned within a certain range via thermal annealing. There have been several reports on SnO₂-based thin-film transistors; however, SnO₂ channels have mostly been deposited with more reactive oxygen sources such as ozone or O₂ plasma [16–18]. For the first time, a working FET has been realized with SnO₂ film deposited using T-ALD with H₂O as reactant. The performance of SnO₂-based FET and its dependence on the conductivity of the channel will be discussed.

On a heavily doped p-type Si substrate, an Al₂O₃ (Thickness = 60 nm) gate dielectric and SnO₂ (Thickness = 6.5 or 9 nm) channel were deposited by T-ALD. Trimethyl aluminum and tetrakisdimethylamine tin were used as precursors and deionized H₂O was used as reactant. The Al₂O₃ layer was deposited at 100 °C with a growth per cycle (GPC) of 1.2 Å/s. SnO₂ was deposited at 200 °C (typical GPC of SnO₂ = 0.43 Å/s) and post-annealed at 400 °C for 1–2 hours in air ambient. A post-annealing step is necessary to improve the conductivity of the SnO₂ film, especially when film is deposited with H₂O. Details of the materials and conductivity can be found in [19]. For the electrical characterization of the SnO₂ films after annealing, the films were also deposited on sapphire. The electrical conductivity of the films was characterized by room-temperature Hall measurement (Ecopia HMS-3000).

SnO₂ FETs(channel length/width = 30/15 µm) were fabricated with a conductive Si substrate as gate electrode. Device structure is schematically shown in Fig. 1(a). After layers were deposited, mesas were formed by wet-etching SnO₂ in HCl solution. The aforementioned post-annealing of SnO₂ was performed after mesa etching because the annealing-induced recrystallization of SnO₂ significantly changed the etching rate. After annealing, a thermal evaporator was used to deposit Ti/Au electrodes as source (S) and drain (D) contacts. Typical process flow is summarized in Fig. 1(b). The fabricated devices were analyzed by a semiconductor parameter analyzer (KEYSIGHT HP4155-C).

Figure 1. (a) Schematic drawing (left) and top-view optical image (right) of SnO₂ FET and (b) process flow for device fabrication.

As mentioned earlier, most oxide semiconductors are intrinsically n-type, with high concentrations of carriers (> 10²⁰ cm⁻³). This makes channel modulation difficult; a film needs to be thin for channel depletion or pinch-off. Typical V_GS-dependent I_DS–V_DS curves of three representative devices are shown in Fig. 2. When the thickness of the SnO₂ channel was 9 nm, I_DS was the highest among devices tested in this study; however, the channel did not adequately pinch off [Fig. 2(a)], even at the estimated Hall carrier concentration of 4.4 × 10¹⁹ cm⁻³ (Table I). The incomplete channel modulation was due to the conduction path from the un-depleted bulk region. The I_DS–V_DS curves provided in Figs. 2(b) and 2(c) show the excellent saturation characteristics of the SnO₂ channels when the thickness is 6.5 nm. Between the two, the 2-hours annealed SnO₂ channel shows 2.5 × higher I_DS than the one with 1-hour annealing at given values of V_DS and V_GS. As can be seen in Table I, Hall analysis of bare samples indicates that the 2-hours annealed sample is more conductive at room temperature, consistent with the device results. It is likely that longer annealing improved the crystalline quality of the layer as well as improving the dielectric/ channel interface. In terms of the interface quality, it is likely that annealing reduced the trap density.

Table 1 . Room temperature Hall measurement results..

SnO2 thickness (nm)	Annealing time (h)	Hall mobility (cm2/V·s)	Hall concentration (× 1019cm3)	Conductivity (Ω−1·cm−1
9.0	2.0	8.1	4.40	57.40
6.5	1.0	2.6	1.21	5.06
6.5	2.0	3.1	1.58	8.05

Figure 2. V_GS-dependent I_DS–V_DS of (a) 9-nm channel with 2-hours annealing, (b) 6.5-nm channel with 2-hours annealing, and (c) 6.5-nm channel with 1-hour annealing.

Figure 3 shows typical transfer curves of the three devices. Figure 3(a) shows that 9-nm-thick SnO₂ film device could not be turned off even at V_GS of -20 V, which was the limit of our semiconductor parameter analyzer. The other two devices, however, turned off at reasonable values of V_GS. Both devices exhibited low leakage current, below the measurement limit (10 nA) of the analyzer, suggesting that I_ON/I_OFF is actually greater than 10⁴. It is also noticeable that the V_GS values at the detection limit were about -5 and -7 V for the 1-hour and 2-hours annealed samples, respectively. While longer annealing improves the crystallinity, it also increases the background carrier concentration within the annealing conditions explored in this work, as suggested by the Hall measurement values in Table I. This increases the threshold voltage as well as the turn-off voltage. The µ_FE values of devices were calculated using Eq. (1):

Figure 3. Transfer curves of (a) 9-nm channel with 2-hours annealing, (b) 6.5-nm channel with 2-hours annealing, and (c) 6.5-nm channel with 1-hour annealing.

where L and W are the length and width of the channel and C_OX is the capacitance of the gate oxide. The highest µ_FE was about 125 cm²/Vs, as shown in Fig. 3(b). This is about 20 % higher than the value of the 1-hour annealed sample, shown in Fig. 3(c). It is noticeable that increasing V_GS increases µ_FE in the linear region. This is likely due to extra charges induced by the gate bias, which can screen charged defects and thereby increase channel conductivity [16]. According to Eq. (1), when everything else is identical, higher µ_FE means a steeper rise of I_DS with increasing V_GS. Therefore, longer annealing duration leads to higher conductance.

The transconductance plots are shown in Fig. 4. The steeper slope from the 2-hours annealed sample has an sub-threshold swing value of 2 V/dec. The SS of the other device is 4 V/dec. This is consistent with other electrical device characterizations. Shih et al. [16] reported SnO₂ FETs (channel thickness/length = 4.5 nm/50 µm) with µ_FE of 147 cm²/Vs, I_ON/I_OFF of ~10^-7, and SS of 110 mV/dec. The reported device incorporated high-k dielectric HfO₂ to improve the overall device performance. Further investigation is necessary to improve SS and understand the discrepancy between the Hall mobility and fieldeffect mobility. Overall, our device is comparable to state-of-the-art SnO₂ FETs, suggesting SnO₂ deposited by T-ALD can be a promising channel material for BEOL-compatible transistors.

Figure 4. Transconductance curves of 2-hours and 1-hour annealed samples.

In conclusion, SnO₂-based FETs were demonstrated in which the SnO₂ channel was deposited by T-ALD with H₂O reactant. Unlike SnO₂ deposited with other oxygen sources such as ozone or O₂ plasma, SnO₂ film deposited using H₂O is very resistive without a post-annealing process. By adjusting the annealing time, it was possible to tune the channel conductivity for FETs. As a result, channel modulation was achieved with excellent pinch-off characteristics from a 6.5-nm thick channel. I_ON/I_OFF and SS were >10⁴ and 2 V/dec, respectively. Under the gate-induced field, the 2-hours annealed SnO₂ channel exhibited electrical properties superior to those of the 1-hour annealed channel. This was attributed to the better crystalline and interfacial qualities. This work demonstrates that SnO₂ and T-ALD can be viable options for realizing high-performance BEOL-compatible oxide transistors.

This work wassupported by the National Research Foundation of Korea (Grant No. NRF-2021R1I1A3054907), funded by the Ministry of Education.

The authors declare no conflicts of interest.