Applied Science and Convergence Technology 2006; 15(6): 630-636
Published online November 1, 2006
Copyright © The Korean Vacuum Society.
S.-H. Nam,J.-S. Hyun,J.-H. Boo
Scale down of semiconductor gate pattern will make progress centrally line width into transistor according to the high integration and high density of flash memory semiconductor. Recently, the many researchers are in the process of developing research for using the ONO(oxide-nitride-oxide) technology for the gate pattern give body to line breadth of less 100 ㎚. Therefore, etch rate and etch profile of the line width detail of less 100 ㎚ affect important factor in a semiconductor process.
In case of increasing of the platen power up to 50 W at the ICP etcher, etch rate and PR selectivity showed good result when the platen power of ICP etcher has 100 W. Also, in case of changing of HBr gas flux at the platen power of 100 W, etch rate was decreasing and PR selectivity is increasing. We founded terms that have etch rate 320 ㎚/min, PR selectivity 3.5:1 and etch slope have vertical in the case of giving the platen power 100 W and HBr gas 35 sccm at the ICP etcher. Also notch was not formed.
Keywords: 유도 결합 플라즈마,식각 속도,감광액 선택비,Platen power,HBr 가스,폴리 실리콘,ICP,Etch rate,PR selectivity,HBr gas,Polysilicon