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## Research Paper

Applied Science and Convergence Technology 2022; 31(6): 145-148

Published online November 30, 2022

https://doi.org/10.5757/ASCT.2022.31.6.145

## Tin Oxide Field-Effect Transistors Deposited by Thermal Atomic Layer Deposition with H2O Reactant

Chanhyeok Park , Seonchang Kim , Gyeong Ryul Lee , and Roy Byung Kyu Chung*

Electronic Materials Science and Engineering, Kyungpook National University, Daegu 41566, Republic of Korea

Correspondence to:roy.b.chung@knu.ac.kr
These authors contributed equally to this work.

Received: October 12, 2022; Revised: October 25, 2022; Accepted: October 28, 2022

In this work, SnO2-based field-effect transistors were fabricated and characterized. SnO2 channel (Thickness = 6.5 or 9.0 nm) was deposited by thermal atomic layer deposition (T-ALD) with H2O as reactant. The conductivity of the channel layer was tuned by a post-annealing process, with annealing temperature limited to 400 ∘C. When the channel thickness was 9 nm, the channel could not be properly modulated due to high intrinsic carrier concentration. On the other hand, a 6.5-nm thick SnO2 channel exhibited excellent device characteristics in general, including clear channel pinch-off and current on/off ratio higher than 104. Increasing the annealing duration from 1 to 2 hours led to higher channel conductivity and transconductance, such that the drain current increased by a factor of 2.5 at the given gate and drain biases. On average, the field-effect mobility increased from 110 to 125 cm2/Vs, and the subthreshold swing decreased from 4 to 2 V/dec. This work demonstrates that SnO2 deposited by T-ALD can be an attractive channel material for back-end-of-line compatible transistors, which are crucial for hyper-scaling of current Si technology.

Keywords: SnO2, Field-effect transistors, Back-end-of-line compatible transistor, Atomic layer deposition

### 1. Introduction

The development of Si technology for processors and memory units has been driven by the scaling down of transistors for better performance, lower power consumption, and higher density. As the channel length of Si metal-oxide-semiconductor field-effect transistors (MOSFETs) reaches its physical limit, however, it is no longer economically feasible to continue MOSFET scale-down [1,2]. Instead, the industry has been developing alternatives such as the through Si-via (TSV), which increases the device density without reducing MOSFET lateral size [3]. Vertically interconnecting devices using a TSV technique means more transistors can be stacked on existing transistors to increase number of devices per unit area. Transistors integrated in such a way are called back-end-of-line (BEOL) compatible transistors, in which ‘compatible’ means the process temperature should not exceed 400–450 °C to protect the underlying devices and interconnecting metals. This constraint on the thermal budget makes it difficult to form high-performance BEOL-compatible transistors by a direct deposition approach [2].

Amorphous/polycrystalline oxide semiconductors such as indium oxide (In2O3), indium-gallium-zinc oxide, and Sn-doped In2O3 have been extensively studied as channel layers for BEOL-compatible transistors because of their excellent electrical conductivity and low process temperature (< 400 °C) [46]. Some promising results have been reported on oxide FETs with current on/off ratio (ION/IOFF) of > 107 and field-effect mobility of 10–20 cm2/Vs [5,7]. However, the scarcity of indium and complicated ternary or quaternary compositions make these oxides unattractive. Tin oxide (SnO and SnO2) is also very attractive because of its large bandgap (3.6 eV) and high intrinsic electron mobility (200–300 cm2/Vs) [8,9]. Furthermore, SnO is known to exhibit p-type conductivity, which is an attractive property for complementary 3-dimensional circuit design [1012].

One of the challenges of using oxide semiconductors, including SnO2, is the doping controllability, because these materials typically contain 1020–1021 cm−3 of electrons from unintentional doping by oxygen vacancies [4,1315]. Such a high concentration of carriers makes channel modulation difficult and can adversely affect channel mobility due to limited channel thickness [5]. In this work, SnO2 was deposited by thermal atomic layer deposition (T-ALD). A typical SnO2 film deposited by T-ALD with H2O reactant is quite resistive without post-annealing. Therefore, its carrier concentration and mobility can be tuned within a certain range via thermal annealing. There have been several reports on SnO2-based thin-film transistors; however, SnO2 channels have mostly been deposited with more reactive oxygen sources such as ozone or O2 plasma [1618]. For the first time, a working FET has been realized with SnO2 film deposited using T-ALD with H2O as reactant. The performance of SnO2-based FET and its dependence on the conductivity of the channel will be discussed.

### 2. Experimental details

On a heavily doped p-type Si substrate, an Al2O3 (Thickness = 60 nm) gate dielectric and SnO2 (Thickness = 6.5 or 9 nm) channel were deposited by T-ALD. Trimethyl aluminum and tetrakisdimethylamine tin were used as precursors and deionized H2O was used as reactant. The Al2O3 layer was deposited at 100 °C with a growth per cycle (GPC) of 1.2 Å/s. SnO2 was deposited at 200 °C (typical GPC of SnO2 = 0.43 Å/s) and post-annealed at 400 °C for 1–2 hours in air ambient. A post-annealing step is necessary to improve the conductivity of the SnO2 film, especially when film is deposited with H2O. Details of the materials and conductivity can be found in [19]. For the electrical characterization of the SnO2 films after annealing, the films were also deposited on sapphire. The electrical conductivity of the films was characterized by room-temperature Hall measurement (Ecopia HMS-3000).

SnO2 FETs(channel length/width = 30/15 µm) were fabricated with a conductive Si substrate as gate electrode. Device structure is schematically shown in Fig. 1(a). After layers were deposited, mesas were formed by wet-etching SnO2 in HCl solution. The aforementioned post-annealing of SnO2 was performed after mesa etching because the annealing-induced recrystallization of SnO2 significantly changed the etching rate. After annealing, a thermal evaporator was used to deposit Ti/Au electrodes as source (S) and drain (D) contacts. Typical process flow is summarized in Fig. 1(b). The fabricated devices were analyzed by a semiconductor parameter analyzer (KEYSIGHT HP4155-C).

Figure 1. (a) Schematic drawing (left) and top-view optical image (right) of SnO2 FET and (b) process flow for device fabrication.

### 3. Results and discussion

As mentioned earlier, most oxide semiconductors are intrinsically n-type, with high concentrations of carriers (> 1020 cm−3). This makes channel modulation difficult; a film needs to be thin for channel depletion or pinch-off. Typical VGS-dependent IDS–VDS curves of three representative devices are shown in Fig. 2. When the thickness of the SnO2 channel was 9 nm, IDS was the highest among devices tested in this study; however, the channel did not adequately pinch off [Fig. 2(a)], even at the estimated Hall carrier concentration of 4.4 × 1019 cm−3 (Table I). The incomplete channel modulation was due to the conduction path from the un-depleted bulk region. The IDS–VDS curves provided in Figs. 2(b) and 2(c) show the excellent saturation characteristics of the SnO2 channels when the thickness is 6.5 nm. Between the two, the 2-hours annealed SnO2 channel shows 2.5 × higher IDS than the one with 1-hour annealing at given values of VDS and VGS. As can be seen in Table I, Hall analysis of bare samples indicates that the 2-hours annealed sample is more conductive at room temperature, consistent with the device results. It is likely that longer annealing improved the crystalline quality of the layer as well as improving the dielectric/ channel interface. In terms of the interface quality, it is likely that annealing reduced the trap density.

Room temperature Hall measurement results..

SnO2 thickness (nm)Annealing time (h)Hall mobility (cm2/V·s)Hall concentration (× 1019cm3)Conductivity (Ω−1·cm−1
9.02.08.14.4057.40
6.51.02.61.215.06
6.52.03.11.588.05

Figure 2. VGS-dependent IDS–VDS of (a) 9-nm channel with 2-hours annealing, (b) 6.5-nm channel with 2-hours annealing, and (c) 6.5-nm channel with 1-hour annealing.

Figure 3 shows typical transfer curves of the three devices. Figure 3(a) shows that 9-nm-thick SnO2 film device could not be turned off even at VGS of -20 V, which was the limit of our semiconductor parameter analyzer. The other two devices, however, turned off at reasonable values of VGS. Both devices exhibited low leakage current, below the measurement limit (10 nA) of the analyzer, suggesting that ION/IOFF is actually greater than 104. It is also noticeable that the VGS values at the detection limit were about -5 and -7 V for the 1-hour and 2-hours annealed samples, respectively. While longer annealing improves the crystallinity, it also increases the background carrier concentration within the annealing conditions explored in this work, as suggested by the Hall measurement values in Table I. This increases the threshold voltage as well as the turn-off voltage. The µFE values of devices were calculated using Eq. (1):

Figure 3. Transfer curves of (a) 9-nm channel with 2-hours annealing, (b) 6.5-nm channel with 2-hours annealing, and (c) 6.5-nm channel with 1-hour annealing.

$μFE=LWCoxVDSdIDSdVGS,$

where L and W are the length and width of the channel and COX is the capacitance of the gate oxide. The highest µFE was about 125 cm2/Vs, as shown in Fig. 3(b). This is about 20 % higher than the value of the 1-hour annealed sample, shown in Fig. 3(c). It is noticeable that increasing VGS increases µFE in the linear region. This is likely due to extra charges induced by the gate bias, which can screen charged defects and thereby increase channel conductivity [16]. According to Eq. (1), when everything else is identical, higher µFE means a steeper rise of IDS with increasing VGS. Therefore, longer annealing duration leads to higher conductance.

The transconductance plots are shown in Fig. 4. The steeper slope from the 2-hours annealed sample has an sub-threshold swing value of 2 V/dec. The SS of the other device is 4 V/dec. This is consistent with other electrical device characterizations. Shih et al. [16] reported SnO2 FETs (channel thickness/length = 4.5 nm/50 µm) with µFE of 147 cm2/Vs, ION/IOFF of ~10-7, and SS of 110 mV/dec. The reported device incorporated high-k dielectric HfO2 to improve the overall device performance. Further investigation is necessary to improve SS and understand the discrepancy between the Hall mobility and fieldeffect mobility. Overall, our device is comparable to state-of-the-art SnO2 FETs, suggesting SnO2 deposited by T-ALD can be a promising channel material for BEOL-compatible transistors.

Figure 4. Transconductance curves of 2-hours and 1-hour annealed samples.

### 4. Conclusions

In conclusion, SnO2-based FETs were demonstrated in which the SnO2 channel was deposited by T-ALD with H2O reactant. Unlike SnO2 deposited with other oxygen sources such as ozone or O2 plasma, SnO2 film deposited using H2O is very resistive without a post-annealing process. By adjusting the annealing time, it was possible to tune the channel conductivity for FETs. As a result, channel modulation was achieved with excellent pinch-off characteristics from a 6.5-nm thick channel. ION/IOFF and SS were >104 and 2 V/dec, respectively. Under the gate-induced field, the 2-hours annealed SnO2 channel exhibited electrical properties superior to those of the 1-hour annealed channel. This was attributed to the better crystalline and interfacial qualities. This work demonstrates that SnO2 and T-ALD can be viable options for realizing high-performance BEOL-compatible oxide transistors.

### Acknowledgments

This work wassupported by the National Research Foundation of Korea (Grant No. NRF-2021R1I1A3054907), funded by the Ministry of Education.

### Conflicts of Interest

The authors declare no conflicts of interest.

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