• Home
  • Sitemap
  • Contact us
Article View

Applied Science and Convergence Technology 1997; 6(2): 103-108

Published online May 1, 1997

Copyright © The Korean Vacuum Society.

Fabrication and characterization of silicon field emitter array with double gate dielectric

Jin Ho Lee,Sung Weon Kang,Yoon-Ho Song,Jong Moon Park,Kyung Ik Cho,Sang Yun Lee,Hyung Joun Yoo

Abstract

Silicon field emitter arrays (PEAs) have been fabricated by a novel method employing a two-step tip etch and a spin-on-glass (SOG) etch-back process using double layered thermal/tetraethylortho-silicate (TEOS) oxides as a gate dielectric. A partial etching was performed by coating a low viscous photo resist and O₂ plasma ashing in order to form the double layered gate dielectric. A small gate aperture with low gate leakage current was obtained by the novel process. The height and the end radius of the fabricated emitter was about 1.1 ㎛ and less than 100 Å, respectively. The anode emission current from a 256 tips array was turned-on at a gate voltage of 40 V. Also, the gate current was less than 0.1% of the anode current.

Share this article on :

Stats or metrics