In the rapidly evolving fields of semiconductor manufacturing and microelectronics, the precision and effectiveness of deep etching processes have become critical to the success of advanced devices [1–3]. As the demand for smaller, more efficient, and highly integrated circuits continues to grow, the ability to precisely etch silicon (Si) structures at a microscopic level is more important than ever [4–7]. Deep etching of Si is not only essential for the fabrication of various microelectronic components and micro-electro-mechanical systems (MEMS) but also plays a crucial role in the development of cutting-edge technologies such as through Si vias and three-dimensional (3D) microelectronic components, which are key drivers of the ‘More than Moore’ trend [8–12].

Despite more than 30 years of extensive research and development, Si deep etching remains a significant challenge. Engineers and researchers are continually striving to maximize microdevice performance, achieve precise control over critical dimensions, and create innovative and original microstructures. The complexity of these demands makes deep etching a persistent and evolving area of focus in the field [10–14].

To address some of the challenges inherent in deep Si etching, the Bosch process was introduced and has since become a widely adopted technique in the industry. Patented in the mid-1990s, the Bosch process operates at ambient temperatures and does not require liquid nitrogen, making it a robust and relatively straightforward choice for industrial applications. The process involves alternating steps of etching and passivation to achieve high-aspect-ratio structures, which are essential for many modern microelectronic devices [11,13,14].

However, the Bosch process is not without drawbacks. Among the primary concerns are issues such as scalloping, where the sidewalls of etched structures exhibit a series of small, periodic indentations due to the alternating etching and passivation steps. Additionally, the process can result in notching at the interface between different layers, particularly at the base of trenches, leading to reliability concerns in the final device [13–16]. These limitations have led to the ongoing exploration of alternative methods that can overcome the inherent challenges of the Bosch process.

One such alternative that has garnered significant attention is cryogenic etching. This technique, which involves etching Si at very low temperatures, presents a compelling solution to some of the problems associated with the Bosch process. Cryogenic etching can achieve smoother sidewalls and reduce the occurrence of defects such as scalloping and notching. Furthermore, it offers better control over the etching profile, allowing for the creation of more precise and complex microstructures [16–20]. As a result, there is a growing recognition of the importance of cryogenic etching in advanced semiconductor manufacturing, particularly as the industry moves towards more demanding applications that require even greater precision and performance.

The aim of this review is to provide a comprehensive exploration of the current state and outcomes of cryogenic etching, not only within the scope of semiconductor manufacturing but also across a wide range of electronic device industries. By examining the limitations of existing techniques, such as the Bosch process, and emphasizing the potential and applicability of cryogenic etching, this paper seeks to illustrate the broader impact of this technique. The review covers its advantages and challenges in various contexts, highlighting how cryogenic etching is positioned to play a crucial role in enabling the next generation of advanced microelectronic devices.

2.1. History background of cryogenic etch

Cryogenic etching is an important technology used in the semiconductor manufacturing process, and generally refers to the process of etching semiconductor materials at very low temperatures (usually below −100 °C). The history of this technology is closely linked to the development of semiconductor technology, and in order to understand its development, it is necessary to look at the following key points in time. The first is when the need for cryogenic etching technology increased and research began. In the 1980s, the need for a process for manufacturing trenches or holes with very high aspect ratios (HARs) in Si emerged. This process was named deep reactive ion etching (DRIE), and its importance also increased with the development of Si vias and 3D microelectronics. Two main technologies were used to perform the DRIE process, the Bosch process and cryogenic etch technology. The Bosch process has been widely used in many studies as a technology that implements a HAR by alternately using passivation gas (e.g., C₄F₈) and etching gas (e.g., SF₆) [21]. However, the Bosch process has disadvantages such as using relatively expensive C₄F₈ gas, showing scalloped sidewalls after etching, and serious contamination of the reactor wall. As researchers seeks to overcome these disadvantages and obtain an etching profile without distortion, interest in cryogenic etch technology has risen [22]. Tachi et al. [23] first reported the application of the low-temperature etching concept to Si in 1988. Tachi et al. [23] maintained the etching temperature environment of the substrate at −100 °C for the DRIE process of Si, and used a mixture of SF₆/O₂ as the etching gas. They reported that during cryogenic DRIE performed under these process conditions, a passivation layer of SiO_xF_y was formed on the etched sidewall, which suppressed isotropic etching and enabled anisotropic etching. In addition, it was reported that w‘hen the temperature of the substrate after etching was increased to room temperature, this passivation layer was naturally desorbed, forming a vertical trench without scalloping [24]. An important point in the cryogenic DRIE process is that the etching process is very sensitive to temperature and oxygen flow. In recent years, interest in Si cryogenic etching has been increasing. However, the fundamental mechanism of how the SiO_xF_y passivation layer is formed and naturally desorbed at temperatures above room temperature is not yet fully understood and, in particular, the problem of how to control the critical dimension of the microstructure has yet to be solved [25].

The next important point in time was the development of cryogenic etching technology. Since the concept of cryogenic etching first appeared in the 1980s, as semiconductor devices became smaller and required higher-resolution patterns, the limitations of the existing plasma etching method became more apparent. Accordingly, researchers widely explored methods to reduce plasma damage and form more precise patterns by performing the etching process in a low or cryogenic environment. In the 1990s, cryogenic etching technology began to be introduced into practical semiconductor manufacturing processes. During this period, cryogenic DRIE technology was used in particular to etch Si and Si oxide (SiO₂) and high anisotropy and low damage could be achieved by performing etching at low temperatures (usually below −100 °C). In the 2000s, as semiconductor technology entered the nanometer (nm) scale, cryogenic etching technology also became more sophisticated. During this period, it was used especially with extreme ultraviolet (EUV) lithography and played an important role in implementing patterns with smaller feature sizes and higher aspect ratios. Cryogenic etching technology has been expanded to more diverse materials since then [26–31], and has been used for etching compound semiconductors such as GaN and GaAs in addition to Si. The significance of this expansion is that this technology is considered an essential process for manufacturing high-frequency devices and power devices [32–35]. Recently, cryogenic etching technology has occupied an increasingly important position in semiconductor manufacturing and its application range is expanding very rapidly [36–42]. In the manufacturing of 3D negative-AND (NAND) flash memory, fin field-effect transistors (FinFETs), and next-generation logic devices, cryogenic etching is recognized as the dominant technology in the device process, and its importance is increasing [43–47]. In addition, along with extreme miniaturization below the nanometer scale, application to new materials is being actively studied. The content related to this research is outlined in Table I.

Table I. Recent studies on cryogenic etch..

Etch materials	Etch gases	Etch temp. (°C)	Ref.
GaN	RIE	−100	[32–35]
SiO2	CF4/H2	−60	[36]
Si nitride (Si3N4)	CF4/H2	−20	[37]
Porous low-k	C4F8/SF6	−140	[38]
Si	nanotube SF6/O2	−110	[39]
Si	SF6/O2	−80 to −120	[40,41]
Si	SF6/O2	−75 to −140	[42]
a-Si, SiO2, and Si3N4	CHF3/Ar	−140	[43]
Si	SF6	20 to −130	[48]
SiO2	C4F8	−90	[49]
SiO2	SF6, SiF4	−100 to −147	[50]
SiO2/Si3N4	HF, methanol	0 to −50	[51]
ONON	F-based	60 to −30	[52]

2.2. Comparison of Bosch process and cryogenic etch

The Bosch process and cryogenic etching are both essential techniques for vertical etching in semiconductor manufacturing. The methods offer their own respective set of advantages and disadvantages, making them suitable for different applications and requirements. This comparison aims to explore the unique characteristics of these technologies and provide a detailed analysis of their differences.

Bosch process

The Bosch process was developed and patented by Robert Bosch GmbH in Germany in the 1990s and was introduced as an improved technology over existing reactive ion etching (RIE). It received considerable attention because it solved the problem of the existing RIE of difficulty in vertically controlling the etching profile while maintaining a HAR. The Bosch process is an etching method that can be divided into an etching process using SF₆ gas and a process of forming a passivation layer (protective layer) using CF series gas, and is designed to form deeper and more vertical structures by repeating this periodically. Due to these etching characteristics, it has served as an important technology in the production of micro devices and has played a very important role in forming vertical structures of Si substrates required for the production of MEMS. The most important characteristic of the Bosch process is that it enables highly anisotropic etching. This is because the formation of a periodic passivation layer controls the etching of the sidewall. In addition, it enables very deep etching. It is suitable for etching deep trenches and microstructures and is established as a very important technology in fields such as MEMS. Finally, it is easy to control the process. Since the etching step and the formation step of the protective film layer can be independently controlled, the depth of various patterns and the shape of the sidewall can be readily adjusted. In contrast to these advantages, the Bosch process also has disadvantages. A well-known disadvantage is that the surface is likely to become rough due to the formation of a step-like structure on the sidewall as the etching of the protective film layer occurs repeatedly. Figure 1 illustrates the etching process according to the process steps of the Bosch process. In a general RIE process, Si is etched by radicals, which are energetic reaction species in the plasma. In this step, isotropic etching characteristics due to a strong chemical reaction appear. In the next step, a polymer layer is formed by the passivation gas, and in the subsequent etching step, vertical etching occurs due to the physical collisions of the high-energy positive ions of the etching gases. These steps are repeated to enable etching of a vertical profile. The profile obtained through this process forms a repetitive pattern, which is called scalloping. This process, however, has the disadvantage that the process time is long. As mentioned above, the overall process time is considerably long because the steps of forming the protective film layer and etching are repeated periodically. Also, it is difficult to set the optimal process conditions. Since the process conditions of the two cyclic steps are repeatedly executed, many experiments and tuning are required to identify conditions that can yield the desired structure while widening the two process windows.

Figure 1. Vertical profile by Bosch process.

Cryogenic process

As mentioned above, cryogenic etching was first applied in the 1980s to address the shortcomings of the Bosch process. In 1988, Tachi et al. [23] applied cryogenic etching technology to the DRIE process of Si. At that time, it was very difficult to obtain anisotropy, high etch rate, and high selectivity with the general RIE process, which was not carried out in a cryogenic environment. Although a high etch rate was confirmed using SF₆ plasma, the etch shape was anisotropic. Anisotropic etching by DRIE could be obtained by mixing gases other than SF₆, such as CF₄/O₂ [36] and SF₆/CHF₃ [44,45], or by mixing these gases with halogen gas (e.g. Br) [46]. However, Tachi et al. [23] were able to obtain anisotropic profiles using existing SF₆ gas by lowering the temperature of the etching environment to −100 °C or lower and proceeding with the process. The underlying goal in the researchers’ process of developing the cryogenic system was to reduce the chemical reaction on the structural side during the plasma etching process by greatly lowering the temperature of the etching environment, while at the same time activating the energetic reaction of ions in the plasma at the bottom of the etching structure. Figures 2 and 3 show the changes in the etching rate of Si and the anisotropic etching characteristics according to the change in the etching environment temperature. Figure 2 presents the change in the etching rate of Si by SF₆, Cl₂, and CF₄ plasma as the etching temperature changes from room temperature to −170 °C. In the case of Cl₂ and CF₄ gases, a change in the etching rate according to the change in temperature was hardly observed. However, in the case of SF₆, the etching rate did not change substantially when the temperature was changed from room temperature to around −140 °C, but the etching rate was reduced to almost zero at −150 °C.

Figure 2. Si etch rates for SF₆, Cl₂, and CF₄ gas plasmas measured as a function of wafer temperature [47], Copyright 1991, AVS Publishing.

Figure 3. Normalized side etch width R, which is defined as R = (side etch width/etch depth) [23], Copyright 1998, AIP Publishing.

This is because the SF₆ gas is adsorbed and frozen on the Si surface due to the effect of the substrate temperature being too low, and consequently the etching reaction does not occur [23,47]. In cryogenic etching, temperature is one of the factors that greatly affects the etching profile. Figure 3 presents results showing the degree of anisotropic etching that occurred while the temperature changed from room temperature to −110 °C. From the results, it can be seen that the anisotropic etching tendency becomes stronger as the temperature decreases [23]. As can be seen from the research results above, cryogenic etching, which proceeds by lowering the temperature of the etching process to −100 °C or lower, enables very precise etching by appropriately controlling physical and chemical reactions in an ultralow temperature environment. The mechanism underlying cryogenic etching is that the low temperature on the substrate promotes the surface adsorption of reactive gases (e.g. SF₆, CxFy, CxHyFz, and etc.), and the ions generated from the plasma reach the Si surface, increasing the reactivity with the etchant, which can increase the etching rate. Furthermore, the byproducts present on the side act as a protective film for a certain period of time and improve the etching profile because they receive relatively less energy from the ions. In addition, the reactive byproducts generated during the cryogenic etching process have low reactivity with the surface of the etchant, and hence are easily removed from the surface, helping to realize high-quality etching with less residue after the process.

In summary, the Bosch process is suitable for applications requiring very deep trenches and microstructures, and can provide anisotropic etching characteristics up to several hundred microns deep, but the roughness of the sidewall and the long process time are disadvantages. On the other hand, cryogenic etching has the advantage of being suitable for etching very smooth sidewall roughness and precise patterns, with a relatively short process time. However, it currently has the disadvantage of requiring substantial cost to control the low substrate temperature at which cryogenic etching is possible, as noted in Table II.

Table II. Comparison of Bosch process and cryogenic etching..

Parameters	Bosch process	Cryogenic etching	Remark
Anisotropy	Excellent	Excellent
Sidewall	can be rough	Smooth	Scalloping for Bosch
Etch depth	Deep etching possible	Relatively shallow etching
Process time	Can be long	Relatively short
Process control	Protective film and etching step control possible	Cryogenic environment control
Cost	Low	High

Cryogenic etching is a crucial process in semiconductor manufacturing, enabling precise control over etch profiles for a variety of applications. It is particularly effective for deep Si etching, where low temperatures facilitate the formation of protective SiO_xF_y layers on sidewalls, ensuring HAR structures. Additionally, in the etching of porous low-K materials, cryogenic conditions reduce plasma-induced damage (PID) by condensing C₄F₈ gas within pores. The process also plays a key role in black Si (b-Si) formation, enhancing surface textures through overpassivation. Furthermore, cryogenic atomic layer etching of SiO₂ allows for atomic-scale precision, which is essential for advanced nanodevices. These diverse applications highlight the significance of cryogenic etching in advancing semiconductor technologies.

3.1. Aspect ratio dependent etching (ARDE) in HAR processes

Recently, the most important etching process in the manufacturing of 3D flash devices among semiconductor devices is the formation of a cylindrical hole inside the film containing the storage device. This process requires alternating etching of ONON (SiO₂/SiNx/SiO₂/SiNx) layers. Initially, gases such as CF₄ and CHF₃ were used to etch these materials, but as the demand for selectivity increased, hydrogen- and carbon-rich gases such as CH₂F₂, CH₃F, C₄F₈, and C₄F₆ have been used. In addition, studies are being conducted to control the deposition rate of CxFy polymers deposited inside the mask and etched structures by adding oxygen and noble gases [53–57]. However, this etching mechanism faces several problems in HAR etching. One is that the flux of neutral species required for polymer formation decreases rapidly as the aspect ratio increases. It is known that only 2.5 % of the inflow flux in a cylindrical structure with an aspect ratio of 50:1 reaches the end of the cylinder due to collisions with the side walls [58]. The ions accelerated by the bias applied to the substrate and the decrease in the number of neutralized ions among these ions upon collision with the side walls of the etching structure severely reduce the etching rate as the aspect ratio increases. This unintended phenomenon is called ARDE.

The most representative phenomenon of ARDE is RIE lag. This refers to a phenomenon where the etch rate decreases as the trench width decreases, and it is known to commonly occur in processes using fluorinated plasma [59,60]. Lai et al. [61] reported that ARDE lag can be reduced or eliminated by fine parameter control of the etching conditions. The results of their study are shown in Figs. 4 and 5. Figure 4 shows normal ARDE lag where the normalized etch rate gradually decreases as the Si trench width decreases. However, it was shown that ARDE lag can be reduced or even inverse ARDE lag can occur in the trench width range (2.5 – 100.0 μm) considered in their study by finely controlling the process conditions such as etching gas and process pressure. Scanning electron microscopy (SEM) images of these three types of lag are shown in Fig. 5. However, the elimination of ARDE lag through changes in these process conditions is expected to have limitations in solving the problem, considering the current process trend in which the trench width is narrowing to the sub-micron level and the diversity and aspect ratio of the etching materials are increasing.

Figure 4. ARDE lags as a function of Si trench width. Reproduced with permission from [48], Copyright 2019, IOP Publishing.

Figure 5. Controlling the ARDE lag. For trenches with width ranging from 2.5 to 10 um under different process conditions: (a) normal ARDE lag (−10 %), (b) elimination of ARDE lag (< 2 %), and (c) inverse ARDE lag (−5 %). Reproduced with permission from [48], Copyright 2019, IOP Publishing.

Another important ARDE phenomenon is that the etch rate depends on the etch depth. This is a phenomenon in which the etch rate decreases as the etching process progresses and the etch depth increases. The cause of ARDE can be explained by the decrease in ion flux reaching the bottom of the etched structure [62–64] and the restricted movement of reactive neutral species [65,66]. Therefore, in order to realize successful HAR etching, it is necessary to ensure the ions and neutral species move with high flux to the inside of the etched structure, as well as to finely adjust the process conditions such as process gas chemistry, input power, and process pressure.

Increased mobility of ions in the etched structure can be achieved by increasing the energy of the accelerated ions [52]. In addition, research is ongoing to maintain high mobility of neutral species high to the bottom of the pattern. In this context, the cryogenic etch process has been receiving the most attention recently. For Si and Si compounds, Shen et al. [52] reported that it is possible to achieve this by using a gas chemistry with high fluorine and hydrogen concentrations as a method to increase the flux of neutral species and maintain the temperature of the substrate at a low temperature. Figure 6 presents the results reported by Shen et al. [52], comparing those obtained under normalized etch rates according to etching depth for conventional etching and low-temperature etching. As shown in the figure, the decrease in etching rate is significantly less in the low-temperature etching environment than in conventional etching. This can be explained by the difference in the amount of movement of ions and neutral species involved in etching when the etching depth increases, as mentioned above.

Figure 6. Normalized etching rate versus depth for conventional and low-temperature etching processes of circular holes with a diameter of 100 nm [52], Copyright 2023, IOP Publishing

The differences between the conventional etching process, which is generally performed at room temperature, and the low-temperature etching process are briefly summarized in Table III. As can be seen in the table, the etching characteristics are very sensitive to changes in the temperature environment, and the changes can be very large. The temperature change causes a difference in the reaction rate between the etching material and the reaction gas, and this difference can greatly affect the etching rate, etching profile, and passivation layer. In particular, many researchers [24,48,67–69] have extensively studied the relatively unique passivation mechanism that appears during etching at low temperatures. Interestingly, it has been reported that the SiO_xF_y passivation layer, which is formed only at extremely low temperatures (typically −100 °C or lower), is mostly removed when the substrate temperature during the process is raised to near room temperature [24,68]. Here, we briefly summarize the results of studies conducted using in-situ ellipsometry and in-situ X-ray photoelectron spectroscopy to observe species desorbed from the substrate surface [48,59–69].

Table III. Variation of etching characteristics with temperature..

Etching characteristics	Low temperature (< −100°C)	High temperature (> 0°C)
Surface reactivity	Increased surface adsorption probability of reaction gas. Effective chemical reaction with plasma.	Reduced adsorption rate. Reduced probability of reaction between plasma and ions.
Passivation layer	Formation of polymer layer in the form of SiOxFy. Fast desorption speed and clean surface.	Slow SiOxFyformation and desorption rates. Rough surface.
Anisotropy	Vertical etching due to increased lateral passivation layer effect.	Isotropic etching increases due to the reduced effect of the lateral passivation layer.
Etch profile	Precise etching characteristics with high reactivity and anisotropic etching characteristics.	Difficulty in precise etching profile control due to low reactivity and anisotropic etching characteristics.
ARDE	Low etch rate reduction according to etch depth and pattern shape.	High etch rate reduction according to etch depth and pattern shape.

The formation and removal of SiO_xF_y molecules can be considered the most important parameter for room temperature and cryogenic etching characteristics, and the results of studies on this by Antoun et al. [48] are shown in Fig. 7. This figure shows the results of observing the thickness of the SiO_xF_y layer deposited on the surface as the substrate temperature changed from 20 to −130 °C using SiF₄/O₂ plasma. The thickness deposited is similar from 20 to −80 °C, but it increases significantly near −100 °C. In addition, the thickness shows a tendency to decrease slightly at lower temperatures. Furthermore, below −130 °C, the polymer was not deposited, but rather the Si was slightly etched. Figure 7 shows the results of the etching rate change of the deposited SiO_xF_y layer according to the substrate temperature change using pure SF₆ plasma. From the results in the figure, it can be seen that the etching rate of the SiO_xF_y deposited on the amorphous Si increases sharply as the substrate temperature decreases to −130 °C.

Figure 7. Thickness of SiO_xF_y passivation layer versus the deposition temperature and the etch rate of the deposited SiO_xF_y layer on an amorphous Si substrate as a function of the substrate temperature. Reproduced with permission from [48], Copyright 2019, IOP Publishing.

In conclusion, in the Si etching process using plasma containing fluorine, the SiO_xF_y passivation layer is mainly formed on the ultralow temperature substrate, and as the temperature decreases below −100 °C, the deposition rate increases and at the same time, it is easy to remove. These low-temperature etching characteristics provide a very clean surface along with HAR etching results and are expected to provide many alternatives for process development required in the future semiconductor process.

3.2. B-Si

B-Si has emerged as a crucial material in the advancement of semiconductor and optoelectronic devices, particularly due to its unique properties that significantly enhance the performance of these devices. The formation of b-Si through cryogenic etching processes, where Si wafers are subjected to SF₆/O₂ plasma under controlled low temperatures, results in a textured surface with micro- and nanostructures that resemble grass. These structures dramatically increase the surface area and reduce reflectivity, which are essential for applications requiring high-efficiency light absorption [15,70–76].

One of the primary applications of b-Si is in the development of high-efficiency solar cells. The increased surface roughness and lighttrapping capabilities of b-Si allow for better absorption of sunlight, which directly translates to higher power conversion efficiencies. Black Si is thus an attractive material for next-generation photovoltaic cells, where maximizing light absorption while minimizing reflection losses is critical to improving overall device performance [70–73] .

Based on these unique features of b-Si, multiple research efforts have demonstrated the impact of cryogenic etching in further enhancing b-Si’s performance in specific applications. Gao et al. [70] employed cryogenic plasma etching to fabricate b-Si, resulting in significant structural and performance enhancements. Figure 8 shows a typical microstructure of b-Si obtained through cryogenic inductively coupled plasma (ICP) RIE, captured via SEM [70]. The SF₆/O₂ gas flow ratios, varied by adjusting the SF₆ and O₂ flow rates, significantly affect the formation of b-Si during the ICP etching process. B-Si does not form when O₂ flow is outside the range of 4 to 20 sccm. Additionally, higher SF₆ concentrations increase the etching rate, promoting faster b-Si formation. The surface exhibits grass-like cone-shaped nanostructures. Savin et al. [71] reported that the unique nanostructure of b-Si allows for highly efficient light absorption, making it particularly advantageous for photovoltaic devices such as solar cells. Figure 9(a) illustrates the external quantum efficiency (EQE) of b-Si solar cells at various angles of incidence. As shown in the figure, b-Si maintains high efficiency over a wide range of incident angles, with minimal drop-off even up to 60 degrees. This is a significant advantage compared to traditional anti-reflection coatings, which are optimized for light incident at perpendicular angles but suffer efficiency losses as the angle of incidence increases. Additionally, Fig. 9(b) demonstrates the change in photocurrent as a function of the angle of incidence, comparing b-Si with a reference cell. The reference cell shows a nearly 4 % reduction in photocurrent at angles beyond 60 degrees, while the b-Si cell experiences less than a 1 % change. This minimal variation in performance highlights b-Si’s ability to induce multiple reflections of light within its nanostructures, ensuring stable absorption regardless of the light’s angle of entry [71].

Figure 8. SEM images with cross-sectional views of b-Si surfaces obtained at different SF₆/O₂ gas flow ratios: (a) 20/20, (b) 34/16, (c) 38/12, (d) 40/10, (e) 42/8, and (f) 46/4 sccm/sccm. All these wafers are etched for 5 min at −120 °C [70], Copyright 2016, ACS Publishing.

Figure 9. Angle-dependent EQE and daily/yearly energy production enhancement. (a) EQE of the b-Si cell for different angles of incidence. (b) Relative photocurrent, with respect to photocurrent at normal incidence, for different light incidence angles for both the b-Si (circles) and reference (squares) solarcells. Light incidence angle θ is defined in the inset. Reproduced with permission from [71], Copyright 2015, Springer Nature.

Additionally, b-Si is being utilized in various photonic devices, such as photodetectors and sensors, where its ability to capture and absorb light more effectively enhances the sensitivity and accuracy of these devices. The overpassivation regime used in cryogenic etching not only helps in creating these microstructures but also stabilizes them, ensuring that the devices maintain their performance over time. This capability is particularly important in applications such as infrared sensors and other advanced optical systems, where precise light management is critical [77–83].

Setälä et al. [79] demonstrated excellent performance of b-Si photodiodes fabricated using cryogenic etching. Specifically, as presented in Fig. 10(a), the b-Si photodiode exhibited near-ideal responsivity across a wide wavelength range from 200 to 1,000 nm. This remarkable performance is attributed to the nanostructures formed through cryogenic etching, which effectively suppressed light reflection, resulting in superior light absorption. Additionally, Fig. 10(b) presents a comparison between the b-Si photodiode and a commercial UV Si photodiode. Setälä et al. [79] reported that b-Si significantly outperformed the commercial device, particularly in the UV wavelength range (200−400 nm). While the commercial Si device showed reduced performance in the UV range, the b-Si maintained near-ideal performance across a broad spectrum due to the enhanced light absorption properties provided by the cryogenic etching process [78,79,82].

Figure 10. (a) Responsivity of a boron-implanted b-Si detector over a wide wave-length range measured at 0 V bias. Dashed line represents one collected electron per a photon. 1/e photon absorption limit for 1.5 μm junction is highlighted. (b) UV responsivity of market leader diffused Si UV photodiodes compared to this work [79], Copyright 2023, ACS Publishing.

In summary, the formation of b-Si via cryogenic etching provides several advantages that have been leveraged across a wide range of applications in both electronics and optoelectronics. The material’s ability to improve light absorption, increase surface area, and maintain structural stability makes it a highly valuable asset in the pursuit of more efficient and advanced semiconductor devices [24,25,77–83]

3.3. Porous low-k materials

Cryogenic etching has emerged as a critical technique in the etching of porous low-k materials, which are increasingly used in advanced semiconductor devices to reduce parasitic capacitance and enhance circuit performance [84,85]. The highly porous structure of these materials, while advantageous for lowering dielectric constants, makes them particularly susceptible to damage during conventional plasma etching processes. PID can significantly degrade the electrical properties and long-term reliability of porous low-k materials by compromising their delicate structure [85–89]. Cryogenic etching mitigates these issues by operating at low temperatures, thereby reducing the chemical and thermal reactivity of the material during etching. This process effectively minimizes PID, preserves the material’s porous architecture, and maintains high selectivity, which is essential for precise patterning in high-density circuits [86–88]. As a result, cryogenic etching not only improves the overall yield of semiconductor manufacturing but also enhances the long-term reliability of devices by maintaining the integrity of the porous low-k layers. Consequently, this technique has become indispensable in the fabrication of next-generation integrated circuits, where maintaining a balance between performance and reliability is paramount.

Chanson et al. [90] presented research on plasma etching processes for porous organosilicate low-k materials. These materials play a critical role in reducing the dielectric constant (k-value), which is essential for minimizing signal delay and power consumption in advanced semiconductor devices. The importance of Si-CH₃ bonds in maintaining the low-k characteristics of organosilicate materials has driven the need for studies focused on minimizing PID during the etching process [86–90]. Chanson et al. [90] propose using high boiling point organic (HBPO) with a micro-capillary condensation mechanism to protect the Si-CH₃ bonds during plasma etching. HBPO is used to mitigate PID by filling the pores in the material at low temperatures, forming a protective layer. This method works efficiently even at temperatures above −50 °C, enabling a wider temperature range for plasma processing compared to extreme cryogenic conditions.

Figure 11(a) illustrates the thickness of the film and the extent of Si-CH₃ damage as a function of temperature, showing how the damage to Si-CH₃ bonds decreases with decreasing temperature. At −50 °C, the equivalent damage layer (EDL) is reduced to nearly negligible levels, demonstrating the effective protection of Si-CH₃ bonds by HBPO, even under high plasma energy conditions. Figure 11(b) shows the change in dielectric constant (k-value) after plasma processing. The figure reveals that at −50 °C, the dielectric constant remains almost unchanged, close to its original pristine value, indicating that the plasma etching process has preserved the material’s electrical performance. This result highlights the success of the process in minimizing Si-CH₃ bond damage while maintaining the integrity of the low-k material’s properties [90,91].

Figure 11. (a) Evolution of film thickness and EDL after 60 s etch using p = 22.5 mTorr, Q(SF₆/HBPO) = 30/4 sccm, P_rf = 500 W, and P_DC = 150 W bias, followed by annealing for 10 min at 400 °C in N₂ (the original thickness was 212 nm). (b) Extracted k-value for the different conditions. The dashed line corresponds to the pristine k-value [90], Copyright 2018, IOP Publishing.

Lopaev et al. [92] reported a study analyzing the impact of nitrogen atom treatment on the Si-CH₃ bonds in organosilicate glass (OSG) films and sought to elucidate the mechanism of PID. The authors investigated how nitrogen atoms interact with Si-CH₃ bonds during plasma processing and observed the extent of damage and the formation of new bonds as a function of temperature.

Figures 12(a)–(c) summarize the results of this experiment. As seen in Fig. 12(a), Lopaev et al. [92] demonstrated that at low temperatures (0 °C), the Si-CH₃ bonds remained relatively intact after nitrogen atom treatment. However, as shown in Fig. 12(b), when the temperature increased to 7 °C, the damage to Si-CH₃ bonds progressively worsened, and new chemical bonds such as Si-CH₂NH started forming. Finally, in Fig. 12(c), at +15 °C, the damage became even more pronounced, with the creation of C-N bonds and –OH groups. This study shows that nitrogen atoms can minimize bond damage at lower temperatures but, as the temperature rises, they tend to damage Si-CH₃ bonds and form new chemical bonds [92].

Figure 12. Differential FTIR spectra of OSG film before and after N atom treatment for the following film temperatures: (a) 0 °С, (b) +7 °С, and (c) +15 °С. The ’+’ sign denotes the appearance of some new spectra features, while the ’−’ sign indicates a decrease of the corresponding bond concentration. A light yellow background highlights typical peaks that appear with N atom adsorption (pore surface nitridation). Reproduced with permission from [92], Copyright 2020, IOP Publishing.

Cryogenic etching technology represents a significant advancement in semiconductor manufacturing, particularly in the precise processing of HAR structures, low-k materials, and sensor applications. It effectively addresses the limitations of the Bosch process, such as scalloping and notching, offering smoother sidewalls and highly precise structural control. By operating in cryogenic conditions, the formation of SiO_xF_y passivation layers enables anisotropic etching, which is critical for the production of highly accurate micro- and nanostructures. Moreover, cryogenic etching provides a powerful solution to minimize PID in porous low-k materials, preserving their electrical properties and ensuring long-term reliability. Techniques such as nitrogen atom treatment have demonstrated the ability to reduce Si- CH₃ bond damage, providing a deeper understanding of temperature-dependent damage mechanisms. Cryogenic etching also shows tremendous potential in the development of high-performance sensors. For instance, b-Si, fabricated using cryogenic etching, exhibits enhanced light absorption due to the formation of nanoscale surface structures. These structures significantly increase the surface area and reduce reflectivity, making b-Si ideal for applications such as solar cells, photodiodes, and infrared sensors. The enhanced light absorption properties directly contribute to improved performance in photonic sensors and optical devices.

This review has covered the historical background and technical benefits of cryogenic etching, emphasizing its practical applications in both semiconductor manufacturing and sensor technologies. The importance of cryogenic etching continues to grow in advanced processes such as 3D NAND, FinFETs, next-generation logic devices, and optical sensors, positioning it as a key technology for future advancements.

In conclusion, cryogenic etching has emerged as an innovative technology that not only overcomes the limitations of conventional processes but also sets new standards in semiconductor and sensor manufacturing. Combined with EUV lithography, it enables the creation of smaller and more complex patterns, further expanding its applicability to new materials and advanced applications. Future research will focus on optimizing cryogenic etching for performance, cost-efficiency, and enhanced sensor functionality, ensuring its pivotal role in the next generation of semiconductor technologies.

The authors declare no conflicts of interest.